1. Field of the Invention
The present invention relates to a semiconductor device which is configured so as to be provided with a resistance element by the use of a conductor layer, and a method of fabricating the same.
2. Description of the Related Art
Japanese patent application publication JP-A-2006-294649 discloses one of the nonvolatile semiconductor storage devices of the above-described type, for example. In the disclosed storage device, a resistance element is provided in a nonvolatile semiconductor storage device having floating gate electrodes, such as a NAND flash memory or a NOR flash memory. In forming the resistance element, a conductor layer for forming floating gate electrodes is formed on a gate insulating film into an elongate resistor. An opening is formed in an intergate insulating film formed on an upper surface of the resistor. A conductor layer is provided for forming control gate electrodes to be formed on an upper portion of the resistor. The conductor layer is divided in the lengthwise direction so that divided conductor layers serve as terminals provided on both ends of the resistor.
When the resistance element is to be set at a higher resistance value in the above-described configuration, a resistivity of the conductor layer for the forming of the floating gate electrodes serving as the resistor is increased, a film thickness or width of the conductor layer as a physical dimension is reduced, or a length of the conductor layer is increased. Since the conductor layer is provided as floating gate electrodes of memory cell transistors, increasing the resistivity or reducing the film thickness is accompanied by changes in the process design. The change in the process design affects the design of memory cell transistors. As a result, it is difficult to design individual transistors so that the transistors achieve respective desired characteristics. Furthermore, it is difficult to employ a method of increasing a resistance value by increasing the length of the conductor layer in the resistor by changes in a layout pattern since the method leads to an increase in an element area.
In view of the above-described problem, reducing the width is desirable as a means that is unaccompanied by an increase in a pattern area or any changes in the process design. In this case, a pattern width of the semiconductor needs to be reduced. However, differing from the memory cell region in which a repeated pattern is formed, a peripheral circuit region in which the resistance element is formed has a minimum width for the patterning by the photolithography process, which minimum width cannot be reduced to such a small value as in the memory cell region.